AMD Geode SC1201 - Manual (Page 215)

AMD Geode™ SC1200/SC1201 Processor Data Book 215
Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0 32579B
Index 9Eh-9Fh Keyboard / Mouse Idle Timer Count Register (R/W) Reset Value: 0000h
15:0 Keyboard / Mouse Idle Timer Count. This idle timer determines when the keyboard and mouse are not in use so that the
LCD screen can be blanked. The 16-bit value programmed in this register represents the period of inactivity for these ports
after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access
occurs to either the keyboard or mouse I/O address spaces (including the mouse serial port address space when a mouse
is enabled on a serial port.)
This counter uses a 1 second time base. To enable this timer, set F0 Index 81h[3] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[3].
Index A0h-A1h User Defined Device 1 Idle Timer Count Register (R/W) Reset Value: 0000h
15:0 User Defined Device 1 (UDEF1) Idle Timer Count. This idle timer determines when the device configured as User Defined
Device 1 (UDEF1) is not in use so that it can be power managed. The 16-bit value programmed in this register represents
the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with
the count value whenever an access occurs to memory or I/O address space configured in the F0 Index C0h (Base Address
register) and F0 Index CCh (Control register).
This counter uses a 1 second time base. To enable this timer, set F0 Index 81h[4] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[4].
Index A2h-A3h User Defined Device 2 Idle Timer Count Register (R/W) Reset Value: 0000h
15:0 User Defined Device 2 (UDEF2) Idle Timer Count. This idle timer determines when the device configured as UDEF2 is not
in use so that it can be power managed. The 16-bit value programmed in this register represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever
an access occurs to memory or I/O address space configured in the F0 Index C4h (Base Address register) and F0 Index
CDh (Control register).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[5] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[5].
Index A4h-A5h User Defined Device 3 Idle Timer Count Register (R/W) Reset Value: 0000h
15:0 User Defined Device 3 (UDEF3) Idle Timer Count. This idle timer determines when the device configured as UDEF3 is not
in use so that it can be power managed. The 16-bit value programmed in this register represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever
an access occurs to memory or I/O address space configured in the UDEF3 Base Address Register (F0 Index C8h) and
UDEF3 Control Register (F0 Index CEh).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[6] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[6].
Index A6h-A7h Video Idle Timer Count Register (R/W) Reset Value: 0000h
15:0 Video Idle Timer Count. This idle timer determines when the graphics subsystem has been idle as part of the Suspend-
determination algorithm. The 16-bit value programmed in this register represents the period of video inactivity after which
the system is alerted via an SMI. The count in this timer is automatically reset at any access to the graphics controller
space.
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[7] = 1.
Since the graphics controller is embedded in the GX1 module, video activity is communicated to the Core Logic module via
the serial connection (PSERIAL register, bit 0). The Core Logic module also detects accesses to standard VGA space on
PCI (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) if an external VGA controller is being used.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[7].
Index A8h-A9h Video Overflow Count Register (R/W) Reset Value: 0000h
15:0 Video Overflow Count. Each time the video speedup counter is triggered, a 100 msec timer is started. If the 100 msec
timer expires before the video speedup counter lapses, the Video Overflow Count register increments and the 100 msec
timer retriggers. Software clears the overflow register when new evaluations are to begin. The count contained in this regis-
ter can be combined with other data to determine the type of video accesses present in the system.
Index AAh-ABh Reserved Reset Value: 00h
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit Description