AMD Geode SC1201 - Manual (Page 171)

AMD Geode™ SC1200/SC1201 Processor Data Book 171
Core Logic Module 32579B
6.2.12.3 VSA Technology Support Hardware
The Core Logic module incorporates the required hard-
ware in order to support the Virtual System Architecture™
(VSA) technology for capture and playback of audio using
an external codec. This eliminates much of the hardware
traditionally associated with industry standard audio func-
tions.
VSA Technology
VSA technology provides a framework to enable software
implementation of traditionally hardware-only components.
VSA software executes in System Management Mode
(SMM), enabling it to execute transparently to the operating
system, drivers and applications.
The VSA design is based upon a simple model for replac-
ing hardware components with software. Hardware to be
virtualized is merely replaced with simple access detection
circuitry which asserts the
SMI# (System Management
Interrupt) internal signal when hardware accesses are
detected. The current execution stream is immediately pre-
empted, and the processor enters SMM. The SMM system
software then saves the processor state, initializes the VSA
execution environment, decodes the SMI source and dis-
patches handler routines which have registered requests to
service the decoded SMI source. Once all handler routines
have completed, the processor state is restored and nor-
mal execution resumes. In this manner, hardware accesses
are transparently replaced with the execution of SMM han-
dler software.
Historically, SMM software was used primarily for the single
purpose of facilitating active power management for note-
book designs. That software’s only function was to manage
the power up and down of devices to save power. With high
performance processors now available, it is feasible to
implement, primarily in SMM software, PC capabilities tra-
ditionally provided by hardware. In contrast to power man-
agement code, this virtualization software generally has
strict performance requirements to prevent application per-
formance from being significantly impacted.
Audio SMI Related Registers
The SMI related registers consist of:
• Audio SMI Status Reporting Registers:
— Top Level SMI Mirror and Status Registers
(F1BAR0+Memory Offset 00h/02h)
— Second Level SMI Status Registers
(F3BAR0+Memory Offset 10h/12h)
• I/O Trap SMI and Fast Write Status Register
(F3BAR0+Memory Offset 14h)
• I/O Trap SMI Enable Register (F3BAR0+Memory Offset
18h)
Audio SMI Status Reporting Registers
The Top SMI Status Mirror and Status registers are the top
level of hierarchy for the SMI Handler in determining the
source of an SMI. These two registers are at
F1BAR0+Memory Offset 00h (Status Mirror) and 02h (Sta-
tus). The registers are identical except that reading the reg-
ister at F1BAR0+Memory Offset 02h clears the status.
The second level of audio SMI status reporting is set up
very much like the top level. There are two status reporting
registers, one “read only” (mirror) and one “read to clear”.
The data returned by reading either offset is the same (i.e.,
SMI was caused by an audio related event). The difference
between F3BAR0+Memory Offset 10h (Status Mirror) and
12h (Status) is in the ability to clear the SMI source at 12h.
Figure 6-14 on page 172 shows an SMI tree for checking
and clearing the source of an audio SMI. Only the audio
SMI bit is detailed here. For details regarding the remaining
bits in the Top SMI Status Mirror and Status registers refer
toTable 6-33 "F1BAR0+I/O Offset: SMI Status Registers"
on page 237.
I/O Trap SMI and Fast Write Status Register
This 32-bit read-only register (F3BAR0+Memory Offset
14h) not only indicates if the enabled I/O trap generated an
SMI, but also contains Fast Path Write related bits.
I/O Trap SMI Enable Register
The I/O Trap SMI Enable register (F3BAR0+Memory Offset
18h) allows traps for specified I/O addresses and config-
ures generation for I/O events. It also contains the enabling
bit for Fast Path Read/Write features.
Status Fast Path Read/Write
Status Fast Path Read – If enabled, the Core Logic module
intercepts and responds to reads to several status regis-
ters. This speeds up operations, and prevents SMI genera-
tion for reads to these registers. This process is called
Status Fast Path Read. Status Fast Path Read is enabled
via F3BAR0+Memory Offset 18h[4].
In Status Fast Path Read the Core Logic module responds
to reads of the following addresses: 388h-38Bh, 2x0h,
2x1h, 2x2h, 2x3h, 2x8h and 2x9h.
Note that if neither sound card or FM I/O mapping is
enabled, then status read trapping is not possible.
Fast Path Write – If enabled, the Core Logic module cap-
tures certain writes to several I/O locations. This feature
prevents two SMIs from being asserted for write operations
that are known to take two accesses (the first access is an
index and the second is data). This process is called Fast
Path Write. Fast Path Write is enabled in via
F3BAR0+Memory Offset 18h[11].
Fast Path Write captures the data and address bit 1 (A1) of
the first access, but does not generate an SMI. A1 is stored
in F3BAR0+Memory Offset 14h[15]. The second access
causes an SMI, and the data and address are captured as
in a normal trapped I/O.