Table 3-2, Bgu481 ball assignment - sorted by ball number – AMD Geode SC1201 User Manual
Page 29
AMD Geode™ SC1200/SC1201 Processor Data Book
29
Signal Definitions
32579B
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
A1
V
SS
GND
---
---
---
A2
V
IO
PWR
---
---
---
A3
AD30
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D6
I/O
IN
PCI
,
O
PCI
A4
PCICLK0
O
O
PCI
V
IO
---
FPCI_MON
I
(PD
100
)
IN
STRP
Strap (See Table 3-
4 on page 44.)
A5
REQ1#
I
(PU
22.5
)
IN
PCI
V
IO
---
A6
PCIRST#
O
O
PCI
V
IO
---
A7
PCICLK
I
IN
T
V
IO
---
A8
IOW#
O
O
3/5
V
IO
PMR[21] = 0 and
PMR[2] = 0
DOCW#
O
O
3/5
PMR[21] = 0 and
PMR[2] = 1
GPIO15
I/O
(PU
22.5
)
IN
TS
,
O
3/5
PMR[21] = 1 and
PMR[2] = 1
A9
GPIO20
I/O
(PU
22.5
)
IN
T
, O
3/5
V
IO
(PMR[23]
3
= 0 and
PMR[7] = 0) or
(PMR[23]
3
= 1 and
PMR[15] = 1 and
PMR[7] = 0)
DOCCS#
O
(PU
22.5
)
O
3/5
(PMR[23]
3
= 0 and
PMR[7] = 1) or
(PMR[23]
3
= 1 and
PMR[15] = 1 and
PMR[7] = 1)
TFTD0
O
(PU
22.5
)
O
1/4
PMR[23]
3
= 1 and
PMR[15] = 0
A10
GPIO17
I/O
(PU
22.5
)
IN
TS
,
O
3/5
V
IO
(PMR[23]
3
= 0 and
PMR[5] = 0) or
(PMR[23]
3
= 1 and
PMR[15] = 1 and
PMR[5] = 0)
IOCS0#
O
(PU
22.5
)
O
3/5
(PMR[23]
3
= 0 and
PMR[5] = 1) or
(PMR[23]
3
= 1 and
PMR[15] = 1 and
PMR[5] = 1)
TFTDCK
O
(PU
22.5
)
O
1/4
PMR[23]
3
= 1 and
PMR[15] = 0
A11
HSYNC
O
O
1/4
V
IO
---
A12
AV
CCCRT
PWR
---
---
---
A13
V
SS
GND
---
---
---
A14
GREEN
O
WIRE
AV
C-
CCRT
---
A15
BLUE
O
WIRE
AV
C-
CCRT
---
A16
V
SS
GND
---
---
---
A17
V
PLL2
PWR
---
---
---
A18
6,
2
PD7
I/O
IN
T
,
O
14/14
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD13
O
O
1/4
PMR[23]
3
= 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
F_AD7
O
O
14/14
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
A19
V
SS
GND
---
---
---
A20
6, 2
PD6
I/O
IN
T
,
O
14/14
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD1
O
O
1/4
(PMR[23]
3
= 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0
VOPD0
O
O
1/4
(PMR[23]
3
= 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
F_AD6
O
O
14/14
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
A21
6, 2
PD1
I/O
IN
T
,
O
14/14
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD7
O
O
1/4
(PMR[23]
3
= 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
VOPD6
O
O
1/4
(PMR[23]
3
= 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
F_AD1
O
O
14/14
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
A22
6, 2
STB#/WRITE#
O
O
14/14
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD17
O
O
1/4
PMR[23]
3
= 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
F_FRAME#
O
O
14/14
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
A23
CVBS
O
WIRE
AV
CCTV
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 356.
Y
O
TVG
O
A24
SVY
O
WIRE
AV
CCTV
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 356.
TVR
O
Cb
O
CVBS
O
A25
TVRSET
I
WIRE
AV
CCTV
---
A26
6
DPOS_PORT3
I/O
IN
USB
,
O
USB
AV
C-
CUSB
---
A27
6
DNEG_PORT3
I/O
IN
USB
,
O
USB
AV
C-
CUSB
---
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration