Kontron AT8404 - Manual (Page 42)

Hardware Description
29 AT8404 User Guide
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The internal Flash memory of the IPMC is divided into two distinct parts, the IPMI firmware and the boot block.
This allows maintaining a permanent boot block and only erasing the IPMI firmware for upgrade procedure.
This is the key feature to achieve a fail-safe upgrade procedure.
The IPMC executes normally the IPMI firmware located in its internal Flash memory. During an update, the
IPMC transfers the new IPMI firmware to one of the two external menory banks. Then, it programs its internal
Flash memory with the new contents of the external memory and restarts. The restart does not affect board
operation in any way. In case of a failure, the IPMC memory is restored from the second external bank. A two-
stage (internal and external) watchdog mechanism enables a reliable fault detection.
3.1.7.2 FPGA
The Field Programmable Gate Array (FPGA) is the central device for all glue logic resources. It is configured
after the management voltages are stable by an external serial Flash device. The FPGA implements the Syn-
chronous Clock Distribution (see section 3.1.5) and is part of the board management. It connects the Unit
Computer to the IPMC and handles the serial interfaces of Unit Computer, IPMC, RTM and the RS232 connector
on the front panel. The FPGA controls the LEDs for the whole board, handles the signals to control and to mon-
itor the AMCs, the RTM and all payload devices connected to the FPGA and it is responsible for the power and
reset sequencing.
The FPGA provides a MultiBoot feature that allows to load one of two FPGA images, either the factory image
or the user image. In combination with a watchdog and fallback mechanism, this allows fail-safe in-field up-
grades of the FPGA code.
3.1.8 RTM Interface
Management and I/O interfaces from the base board are routed to Zone 3 where a connector mates with the
RTM. This allows base boards to be quickly and reliably serviced without the issues associated with disconnect-
ing and reconnecting multiple cable assemblies. The RTM connection is compliant to the PICMG 3.0 standard.
For the connection between the AT8404 and the RTM, three connectors with 40 differential pairs are used
(J30, J31 and J32).
Each AMC Bay has seven generic interconnects to the RTM Zone 3. Two SAS/SATA interfaces for mass storage
are implemented. There is a JTAG connection for FPGA update or Boundary Scan-Test. An I²C IPMI interface is
implemented for board management. The Unit Computer’s management interfaces (Fast Ethernet and RS232)
are also connected to the RTM. A GbE port allows connection to the GbE switch.