ADLINK nanoX-BT - Manual (Page 22)

Page 22 nanoX-BT
3.3.10. USB 3.0 Extension
Signal Pin Description I/O PU/PD Comment
USB_SSRX0-
USB_SSRX0+ A22
A23 Additional Receive signal differential pairs for the SuperSpeed
USB data path on USB0 I PCIE
USB_SSTX0-
USB_SSTX0+ B22
B23 Additional Transmit signal differential pairs for the SuperSpeed
USB data path on USB0 O PCIE AC coupled on Module
USB_SSRX1-
USB_SSRX1+ A25
A26 Additional Receive signal differential pairs for the SuperSpeed
USB data path on USB1 I PCIE Not supported
USB_SSTX1-
USB_SSTX1+ B25
B26 Additional Transmit signal differential pairs for the SuperSpeed
USB data path on USB1 O PCIE Not supported
3.3.11. USB Root Segmentation
XHCI Controller
Port 0
(1/2.0)
USB
0-
/ A45
USB0
+
/ A4
6
USB
1-
/ B45
USB1
+
/ B4
6
USB
2-
/ A42
USB2
+
/ A4
3
USB
3-
/ B42
USB3
+
/ B4
3
USB
7-
/ B36
USB7
+
/ B3
7
EHCI Controller
P1 P2 P3 P4 P1-P4
SSP
1
P4
Port 1
(1/2.0)
Port 2
(1/2.0)
Port 3
(1/2.0)
Port 7
Client
P5
Port 0
(3.0)
U
S
B_SS
R
X
0-
/A
22
USB_
SSRX0
+ /A2
3
USB
_SST
X0
-/
B2
2
USB_S
STX0
+
/B
23
ULPI
3.3.12. SPI (BIOS only)
Signal Pin # Description I/O PU/PD Comment
SPI_CS# B97 Chip select for Carrier Board SPI BIOS Flash. O 3.3VSB Only supports CS0
SPI_MISO A92 Data in to module from carrier board SPI BIOS flash. I 3.3VSB
SPI_MOSI A95 Data out from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash. O 3.3VSB
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module – nominally
3.3V.
The Module shall provide a minimum of 100mA on SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices on the Carrier O P 3.3VSB
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K
3.3V Carrier shall pull to
GND or leave not
connected
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I PU 10K
3.3V Carrier shall pull to
GND or leave not
connected