Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 23)

Chapter 6: Board Test System 6–5
Using the Board Test System
August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition
User Guide
■ PSO —Sets the MAX II PSO register. The following options are available:
■ Use PSR —Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
■ Use PSS —Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
■ PSS —Displays the MAX II PSS register value.
■ PSR —Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to Table 6–1
for more information.
1 Because the System Info tab requires that a specific design is running in the FPGA at
a specific clock speed, writing a 0 to SRST; or changing the PSO value can cause the
Board Test System to stop running.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Stratix V GX device is always the first device in the chain.
1
MAX_JTAG_EN (J62) includes the MAX II device in the JTAG chain when a jumper is
not installed. To remove the MAX II device from the chain, install a jumper to J62.