Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 34)

6–16 Chapter 6: Board Test System
The Clock Control
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
User Guide
The Clock Control communicates with the MAX II device on the board through the
JTAG bus.
Figure 6–8 shows the Clock Control.
The following sections describe the Clock Control controls.
Clock Tabs
There are three tabs to control each clock generator device. The U53 Si5338 tab
controls the clocks to the Stratix V fabric clock input and the reference clocks for all
the optical interfaces. The default is 100 MHz for the fabric and 644.53125 MHz for the
reference clocks for the transceivers. The U44 Si5338 tab controls the clocks for the
DDR3 and the Interlaken interface; its default is 100MHz for the DDR3 interface and
625MHz for the Interlaken interface. The U22 Si5338 tab controls the clocks for the
QDR II interface and the transceivers for the optical interfaces. The default
frequencies for these interfaces are 100MHz for the QDR II interface and
644.53125 MHz for the transceivers.
Registers
The Registers control shows the current values from the clock driver.
Frequency
Enter the desired frequencies for each CLK. The range of this GUI is from 5 MHz to
710 MHz. There are some limitations for what frequency combinations are allowed.
Disable
The Disable controls enables and disables all or selected outputs of the clock
generators.
Figure 6–8. The Clock Control