Default, Set new frequency, Before configuring – Altera Arria V SoC User Manual

Page 39: Configuring the fpga, Default –19 set new frequency –19, Before configuring –19 configuring the fpga –19

Advertising
background image

Chapter 5: Board Test System

5–19

Configuring the FPGA Using the Quartus II Programmer

June 2014

Altera Corporation

Arria V SoC Development Kit

User Guide

Default

This control sets the frequency for the oscillator associated with the active tab back to
its default value. This can also be accomplished by power cycling the board.

Set New Frequency

The Set New Frequency control sets the programmable oscillator frequency for the
selected clock to the value in the Target frequency control for the programmable
oscillators. Frequency changes might take several milliseconds to take effect. You
might see glitches on the clock during this time. Altera recommends resetting the
FPGA logic after changing frequencies.

f

For more information about these programmable oscillators, refer to the data sheets
available on the Silicon Labs website (

www.silabs.com

).

Configuring the FPGA Using the Quartus II Programmer

You can use the Quartus II Programmer to configure the FPGA with your SRAM
Object File (.sof) file.

Before Configuring

Ensure the following:

The Quartus II Programmer and the USB-Blaster II driver are installed on the host
computer.

The USB cable is connected to the development board.

Power to the board is on, and no other applications that use the JTAG chain are
running.

If the Quartus II Programmer window is already open, and you power cycle the
board, to detect the JTAG chain, do the following:

Click Hardware Setup in the Quartus II Programmer window.

Reselect USB-Blaster II in order to properly detect the JTAG chain.

Configuring the FPGA

Perform these steps:

1. Start the Quartus II Programmer.

2. Click Auto Detect to display the devices in the JTAG chain.

3. Click Add File and select the path to the desired .sof.

4. Turn on the Program/Configure option for the added file.

5. Click Start to download the selected file to the FPGA. Configuration is complete

when the progress bar reaches 100%.

Advertising