Altera PowerPlay Early Power Estimator - Manual (Page 27)

Chapter 3: Using Cyclone III PowerPlay Early Power Estimator 3–15
PowerPlay Early Power Estimator Inputs
© June 2009 Altera Corporation PowerPlay Early Power Estimator User Guide for Cyclone III FPGAs
Figure 3–8 shows the I/O section of the PowerPlay Early Power Estimator and the
estimated power consumed by the I/O pins.
Phase-Locked Loops
Cyclone III device family feature fast phase-locked loops (PLLs).
Each row in the PLL section represents one or more PLLs in the device. You need to
enter the maximum output frequency and the VCO frequency for each PLL.
Table 3–7 describes the values that need to be entered in the PLL section of the
PowerPlay Early Power Estimator.
Figure 3–8. PowerPlay Early Power Estimator I/O Section
Table 3–7. PLL Section Information
Parameters Description
Module Enter a name for the PLL in this column. This is an optional value.
# PLL Blocks Enter the number of PLL blocks with the same specific output frequency and VCO frequency
combination.
Output Freq (MHz) Enter the maximum output frequency (f
MAX
) of the PLL (in MHz). The maximum output frequency
is reported in the Output Frequency column of the Quartus II Compilation Report. In the
Compilation Report, select Fitter, and click Resource Section. Select PLL Usage, and click
Output Frequency.
If there are multiple clock outputs from the PLL, choose the maximum output frequency listed.
VCO Freq (MHz) Enter the frequency of the voltage controlled oscillator in MHz. The VCO frequency is reported in
the Nominal VCO frequency row of the Quartus II Compilation Report. In the Compilation
Report, select Fitter, and click Resource Section. Select PLL Summary, and click Nominal VCO
frequency.
Total Power (W) This shows the estimated combined power for V
CCA
and V
CCD
(in W), based on the maximum
output frequency and the VCO frequency you entered. This value is calculated automatically.
User Comments Enter any comments. This is an optional entry.