Altera Stratix IV GX FPGA - Manual (Page 34)

6–10 Chapter 6: Board Test System
Using the Board Test System
Stratix IV GX FPGA Development Kit User Guide March 2014 Altera Corporation
The DDR3 Tab
The DDR3 tab allows you to read and write the DDR3 memory on your board.
Figure 6–5 shows the DDR3 tab.
The following sections describe the controls on the DDR3 tab.
Port
The Port control directs communication to one of two DDR3 memory ports on your
board. A 16-bit interface connects to the top bank of the Stratix IV GX FPGA and a 64-
bit interface connects to the bottom banks of the FPGA.
Start
The Start control initiates DDR3 memory transaction performance analysis.
Stop
The Stop control terminates transaction performance analysis.
Figure 6–5. The DDR3 Tab