Altera Stratix IV GX FPGA - Manual (Page 47)

Chapter 6: Board Test System 6–23
The Clock Control
March 2014 Altera Corporation Stratix IV GX FPGA Development Kit User Guide
The Clock Control communicates with the MAX II device on the board through the
JTAG bus. The Si570 programmable oscillator is connected to the MAX II device
through a 2-wire serial bus.
Figure 6–11 shows the Clock Control.
The following sections describe the Clock Control controls.
Serial Port Registers
The Serial port registers control shows the current values from the Si570 registers.
f
For more information about the Si570 registers, refer to the Si570/Si571 data sheet
available on the Silicon Labs website (
www.silabs.com ).
fXTAL
The fXTAL control shows the calculated internal fixed-frequency crystal based on the
serial port register values.
f
For more information about the f
XTAL
value and how it is calculated, refer to the
Si570/Si571 data sheet available on the Silicon Labs website ( www.silabs.com ).
Disable Oscillator
The Disable oscillator enables and disables the Si570 output buffer. Turn on Disable
oscillator
to power down the Si570 output buffer. Turn off the Disable oscillator to
drive the Si570 output buffer normally.
Figure 6–11. The Clock Control