Altera Stratix IV GX FPGA - Manual (Page 55)

March 2014 Altera Corporation Stratix IV GX FPGA Development Kit User Guide
Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
Date Version Changes
March 2014 2.2
■ Added programming clarification in Appendix A for those who have the older dual-die CFI
flash. Use one base address for hw.flash and another for sw.flash.
■ Corrected board label for SW4 ( Table 4–2 ) .
June 2010 2.1
■ Changed software distribution method.
■ Changed dual-die CFI flash memory device to single-die.
November 2009 2.0
Engineering silicon to production silicon revisions:
■ Revised BTS screen shots to reflect minor GUI revisions.
■ The Configure menu now offers options to determine how to pass data through the
JTAG chain.
■ The Config tab MAX II controls are now more obvious.
■ Changed board update portal .sof name from stratixIVGX_4sgx230es_dev_bup.sof to
s4gx230_fpga_bup.sof.
■ Changed directory path name from stratixIVGX_4sgx230es_fpga to
stratixIVGX_4sgx230_fpga.
■ Changed PowerTool.exe to PowerMonitor.exe.
■ Added description of the Clock Control stand-alone application.
■ Added instructions in Appendix A about restoring the board’s MAC address.
June 2009 1.1
■ Added description of factory board switch settings.
■ Added instructions to restore MAX II CPLD to factory settings.
May 2009 1.0 Initial release.