About this kit, Kit features, Hardware – Altera Stratix IV GX FPGA User Manual

Page 7

Advertising
background image

March 2014 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

1. About This Kit

The Altera

®

Stratix

®

IV GX FPGA Development Kit is a complete design environment

that includes both the hardware and software you need to develop Stratix IV GX
FPGA designs. The PCI-SIG-compliant board and the one-year license for the
Quartus

®

II software provide everything you need to begin developing custom

Stratix IV GX FPGA designs. The following list describes what you can accomplish
with the kit:

Develop and test PCI Express

®

(PCIe) 2.0 designs

Develop and test memory subsystems consisting of DDR3 and QDR II+ memories

Build designs capable of migrating to Altera’s low-cost HardCopy

®

IV ASICs

Take advantage of the modular and scalable design by using the high-speed
mezzanine card (HSMC) connectors to interface to over 20 different HSMCs
provided by Altera partners, supporting protocols such as Serial RapidIO

®

,

10 Gigabit Ethernet, SONET, Common Public Radio Interface (CPRI), Open Base
Station Architecture Initiative (OBSAI) and others

Develop FPGAs design for cost-sensitive applications

Measure the FPGA's low power consumption

Kit Features

This section briefly describes the Stratix IV GX FPGA Development Kit contents.

Hardware

The Stratix IV GX FPGA Development Kit includes the following hardware:

Stratix IV GX FPGA development board—A development platform that allows
you to develop and prototype hardware designs running on the Stratix IV GX
EP4SGX230 FPGA.

f

For detailed information about the board components and interfaces, refer
to the

Stratix IV GX FPGA Development Board Reference Manual

.

HSMC loopback board—A daughtercard that allows for loopback testing all
signals on the HSMC interface using the Board Test System

HSMC debug breakout board—A daughtercard that routes 40 CMOS signals to a
0.1" header and adds 20 LEDs to the remaining 40 CMOS signals.

Advertising