Altera Stratix IV GX FPGA - Manual (Page 39)

Chapter 6: Board Test System 6–15
Using the Board Test System
March 2014 Altera Corporation Stratix IV GX FPGA Development Kit User Guide
The following sections describe the controls on the HSMC tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Port
The Port control allows you to specify the type of test to run on the HSMC ports. The
following HSMC port tests are available:
■ HSMA x4 Transceivers [0..3]
■ HSMA x4 Transceivers [4..7]
■ HSMB x4 Transceivers [0..3]
■ HSMB x2 Transceivers [4..5]
■ HSMA x17 LVDS SERDES
■ HSMB x17 LVDS SERDES
■ HSMA x3 Single Ended Loopback
■ HSMB x3 Single Ended Loopback
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS —Selects pseudo-random bit sequences.
■ Memory —Selects a generic data pattern stored in the on chip memory of the
Stratix IV GX device.
■ Math —Selects data generated from a simple math function within the FPGA
fabric.
Error Control
The following controls display data errors detected during analysis and allow you to
insert errors:
■ Detected errors —Displays the number of data errors detected in the hardware.
■ Inserted errors —Displays the number of errors inserted into the transmit data
stream.
■ Insert Error —Inserts a one-word error into the transmit data stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear —Resets the Detected errors and Inserted errors counters to zeros.