Altera Stratix IV GX FPGA - Manual (Page 40)

6–16 Chapter 6: Board Test System
Using the Board Test System
Stratix IV GX FPGA Development Kit User Guide March 2014 Altera Corporation
Start
The Start control initiates HSMC transaction performance analysis.
Stop
The Stop control terminates transaction performance analysis.
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
■ TX and RX performance bars—Show the percentage of maximum theoretical data
rate that the requested transactions are able to achieve.
■ Tx (MBps) and Rx (MBps)—Show the number of bytes of data analyzed per
second. The transceiver buses are 4 bits (serial channels) wide and clocked using
the 100 MHz oscillator with a PLL multiplier of 20, so the data rate is 2 Gbps,
totaling 8 MBps per transceiver port. The LVDS SERDES bus is 17 bits wide. The
HSMC x17 SERDES buses on both HSMC A and HSMC B are 17 bits wide and
clocked using the 125 MHz oscillator with a PLL multiplier of 13, equating to a
1.625 Gbps per pin, or a 27.625 Gbps bandwidth for each x17 SERDES port. The x3
single-ended data bus is 3 bits wide and clocked using a 50 MHz clock single-data-
rate for 50 Mbps per pin, or a 150 Mbps bandwidth for each x3 single-ended data
port.
1
Performance figures are based on a 100-MHz input clock from
programmable oscillator X6. Using the
“The Clock Control” on page 6–22 to
adjust the frequency changes the circuit speed in real time and the HSMC
tab performance indicators, which are capped at 100% for increased
frequencies. Physical layer speeds equal the oscillator X6 frequency times
the input PLL multiplier ratio. The default is 2 GHz (100 MHz × 20) or
2 Gbps per pin or 8 Gbps total. Changing the oscillator X6 frequency to
400 MHz changes the circuit speed to 8 GHz or 32 Gbps total. Typically you
need to reset the HSMC design after changing the clock frequency.
1 The HSMC x17 SERDES and x3 single-ended ports use fixed frequency
oscillators and are not affected by the Clock Control application.