Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 14)

2–6 Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Arria II GX FPGA Development Board, 6G Edition Reference Manual © July 2010 Altera Corporation
Table 2–4 lists the I/O count for the EP2AGX125 and EP2AGX260 device.
Table 2–5 lists the Arria II GX device pin count and usage by function on the
development board.
MAX II CPLD EPM2210 System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Virtual JTAG interface for PC-based GUI
■ Control registers for clocks
■ Control registers for remote system update
Table 2–4. I/O Count for the EP2AGX125 and EP2AGX260 Device
Package Device
Bank
Total (1) 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B
1152-pin Flip Chip
FBGA EP2AGX125 70 — 74 16 66 — 66 — 70 16 74 — 452
EP2AGX260 70 32 74 32 66 32 66 32 70 32 74 32 612
Note to Table 2–4 :
(1) Transceiver signals are not included.
Table 2–5. Arria II GX Device Pin Count and Usage
Function I/O Standard I/O Count Special Pins
DDR3 ×16 Port 1.5-V SSTL 49 2 Diff ×8 DQS
DDR2 SODIMM ×64 Port 1.8-V SSTL 120 8 Diff ×8 DQS
MAX Bus 1.5-V CMOS 8 —
Flash, SRAM, FSM Bus 2.5-V CMOS 82 —
PCI Express ×8 2.5-V CMOS + XCVR 41 1 REFCLK, 8 XCVR
HSMC Port A 2.5-V CMOS + LVDS + XCVR 104 4 XCVR, 17 LVDS, 5 Clock Inputs
HSMC Port B (1) 2.5-V CMOS + XCVR 102 4 XCVR, 1 Clock Input
Gigabit Ethernet 2.5-V CMOS + LVDS 16 1 Clock Input
Buttons 1.8-V + 2.5-V CMOS 3 1 DEV_CLRn
Switches 2.5-V CMOS 4 —
LCD 2.5-V CMOS 11 —
LEDs 2.5-V CMOS 7/9 (1) —
Clocks or Oscillators 2.5-V CMOS + LVDS + LVPECL 13/15 (1) 5 REFCLK
Device I/O Total: 458/564 (1)
Note to Table 2–5 :
(1) The HSMC port B is populated when the board uses an EP2AGX260 device. To support the HSMC port B, there are two additional LEDs and a
REFCLK in quadrant 3.