Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 15)

Chapter 2: Board Components 2–7
MAX II CPLD EPM2210 System Controller
© July 2010 Altera Corporation Arria II GX FPGA Development Board, 6G Edition Reference Manual
Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality
and external circuit connections as a block diagram.
Table 2–6 lists the I/O signals present on the MAX II CPLD EPM2210 System
Controller. The signal names and functions are relative to the MAX II device (U32).
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
Information
Register
Embedded
Blaster
MAX-II
Power
Calculations
SLD-HUB
PFL
Power
Measurement
Results
Virtual-JTAG
PC
A2GX
LTC2418
Controller
FLASH
Decoder Encoder
GPIO
JTAG Control
SSRAM
Control
Register
Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 5)
Schematic Signal Name I/O Standard
EPM2210
Pin Number
EP2AGX125
Pin Number
Description
clk_enable 2.5-V K14 — DIP - clock oscillator enable
clk_sel 2.5-V P2 — DIP - clock select SMA or oscillator
clk1_ce 2.5-V N3 — Programmable oscillator 1 chip select
clk1_od[0] 2.5-V M2 — Programmable oscillator 1 output divider 0
clk1_od[1] 2.5-V M1 — Programmable oscillator 1 output divider 1
clk1_od[2] 2.5-V L3 — Programmable oscillator 1 output divider 2
clk1_os[0] 2.5-V N1 — Programmable oscillator 1 output select 0
clk1_os[1] 2.5-V N2 — Programmable oscillator 1 output select 1
clk1_pr[0] 2.5-V L2 — Programmable oscillator 1 prescaler 0
clk1_pr[1] 2.5-V L1 — Programmable oscillator 1 prescaler 1
clk1_rstn 2.5-V M3 — Programmable oscillator 1 reset
clk100_cpld 2.5-V H12 — 100 MHz clock input
clk155_oe 2.5-V E1 — 155.52 MHz oscillator enable
clk2_ce 2.5-V M14 — Programmable oscillator 2 chip select
clk2_od[0] 2.5-V N16 — Programmable oscillator 2 output divider 0
clk2_od[1] 2.5-V N14 — Programmable oscillator 2 output divider 1
clk2_od[2] 2.5-V N13 — Programmable oscillator 2 output divider 2