Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 37)

Chapter 2: Board Components 2–29
Components and Interfaces
© July 2010 Altera Corporation Arria II GX FPGA Development Board, 6G Edition Reference Manual
J14.B37 Add-in card receive bus PCIE_RX_P5
1.5-V PCML
AC33
J14.B38 Add-in card receive bus PCIE_RX_N5 AC34
J14.B41 Add-in card receive bus PCIE_RX_P6 AA33
J14.B42 Add-in card receive bus PCIE_RX_N6 AA34
J14.B45 Add-in card receive bus PCIE_RX_P7 W33
J14.B46 Add-in card receive bus PCIE_RX_N7 W34
J14.A16 Add-in card transmit bus PCIE_TX_P0 AM31
J14.A17 Add-in card transmit bus PCIE_TX_N0 AM32
J14.A21 Add-in card transmit bus PCIE_TX_P1 AK31
J14.A22 Add-in card transmit bus PCIE_TX_N1 AK32
J14.A25 Add-in card transmit bus PCIE_TX_P2 AH31
J14.A26 Add-in card transmit bus PCIE_TX_N2 AH32
J14.A29 Add-in card transmit bus PCIE_TX_P3 AF31
J14.A30 Add-in card transmit bus PCIE_TX_N3 AF32
J14.A35 Add-in card transmit bus PCIE_TX_P4 AD31
J14.A36 Add-in card transmit bus PCIE_TX_N4 AD32
J14.A39 Add-in card transmit bus PCIE_TX_P5 AB31
J14.A40 Add-in card transmit bus PCIE_TX_N5 AB32
J14.A43 Add-in card transmit bus PCIE_TX_P6 Y31
J14.A44 Add-in card transmit bus PCIE_TX_N6 Y32
J14.A47 Add-in card transmit bus PCIE_TX_P7 V31
J14.A48 Add-in card transmit bus PCIE_TX_N7 V32
J14.A13 Motherboard reference clock PCIE_REFCLK_P
HCSL
AE29
J14.A14 Motherboard reference clock PCIE_REFCLK_N AE30
J14.A11 Reset PCIE_PERSTn
LVTTL
N1
J14.B11 Wake signal PCIE_WAKEn C30
J14.B5 SMB clock PCIE_SMBCLK M18
J14.B6 SMB data PCIE_SMBDAT D27
— x1 Presence detect PCIE_LED_X1 C28
— x4 Presence detect PCIE_LED_X4 D26
— x8 Presence detect PCIE_LED_X8 C27
Table 2–33. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board Reference Description
Schematic Signal
Name I/O Standard
Arria II GX Device
Pin Number