Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 43)

Chapter 2: Board Components 2–35
Components and Interfaces
© July 2010 Altera Corporation Arria II GX FPGA Development Board, 6G Edition Reference Manual
Table 2–37 lists the HSMC port B interface pin assignments, signal names, and
functions.
J2.160 HSMC port A presence detect HSMA_PSNT_n
2.5-V
U3
D4 User LED to show RX data activity on
HSMC port A HSMA_RX_LED N5
D5 User LED to show TX data activity on
HSMC port A HSMA_TX_LED C29
Table 2–36. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board
Reference Description
Schematic Signal
Name I/O Standard
Arria II GX
Device
Pin Number
Table 2–37. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference Description
Schematic Signal
Name I/O Standard
Arria II GX
Device
Pin Number
J1.17 Transceiver TX bit 3 HSMB_TX_P3
1.5-V PCML
B31
J1.18 Transceiver RX bit 3 HSMB_RX_P3 C33
J1.19 Transceiver TX bit 3n HSMB_TX_N3 B32
J1.20 Transceiver RX bit 3n HSMB_RX_N3 C34
J1.21 Transceiver TX bit 2 HSMB_TX_P2 D31
J1.22 Transceiver RX bit 2 HSMB_RX_P2 E33
J1.23 Transceiver TX bit 2n HSMB_TX_N2 D32
J1.24 Transceiver RX bit 2n HSMB_RX_N2 E34
J1.25 Transceiver TX bit 1 HSMB_TX_P1 F31
J1.26 Transceiver RX bit 1 HSMB_RX_P1 G33
J1.27 Transceiver TX bit 1n HSMB_TX_N1 F32
J1.28 Transceiver RX bit 1n HSMB_RX_N1 G34
J1.29 Transceiver TX bit 0 HSMB_TX_P0 H31
J1.30 Transceiver RX bit 0 HSMB_RX_P0 J33
J1.31 Transceiver TX bit 0n HSMB_TX_N0 H32
J1.32 Transceiver RX bit 0n HSMB_RX_N0 J34
J1.33 Management serial data HSMB_SDA
2.5-V
AK27
J1.34 Management serial clock HSMB_SCL AJ27
J1.35 JTAG clock signal JTAG_TCK L24
J1.36 JTAG mode select signal JTAG_TMS N25
J1.37 JTAG data output JTAG_HSMB_TDO —
J1.38 JTAG data input JTAG_HSMB_TDI —
J1.39 Dedicated CMOS clock out HSMB_CLKOUT0 AG30
J1.40 Dedicated CMOS clock in HSMB_CLKIN0 AP16
J1.41 Dedicated CMOS I/O bit 0 HSMB_D0 AH29
J1.42 Dedicated CMOS I/O bit 1 HSMB_D1 AH30
J1.43 Dedicated CMOS I/O bit 2 HSMB_D2 AK30