Altera Nios Development Board Cyclone II Edition - Manual (Page 43)

Altera Corporation Reference Manual 2–31
May 2007 Nios Development Board Cyclone II Edition
Board Components
Table 2–16 shows the pin out information for J25. Unless otherwise noted,
labels indicate FPGA pin numbers.
Test Points
(TP1 – TP8) TP1 – TP8 are test points connected to I/O pins on the FPGA. FPGA
designs can route signals to these I/O pins to be probed. TP1 –TP8 also
connect to the configuration controller (U3).
Table 2–16. Mictor Connector Pin Table
FPGA Pin J25 Pin Board Net Name
V21 5 mictor_clk
AC8 38 mictor0
AD8 36 mictor1
W10 34 mictor2
Y10 32 mictor3
V10 30 mictor4
V9 28 mictor5
AD6 26 mictor6
AD7 24 mictor7
AE5 22 mictor8
AF5 20 mictor9
AD4 18 mictor10
AD5 16 mictor11
AC5 10 mictor12
AC6 8 mictor13
AF4 37 mictor14
AE4 35 mictor15
B21 33 mictor16
B22 31 mictor17
A22 29 mictor18
A23 27 mictor19
B23 25 mictor20
D21 23 mictor21
C21 13 mictor22
C22 9 mictor23
C23 7 mictor24
B25 6 mictor_trclk