Altera Stratix II EP2S180 DSP Development Board - Manual (Page 42)

2–34 Core Version a.b.c variable Altera Corporation
Stratix II EP2S180 DSP Development Board Reference Manual
Board Components
■ Pin 41 of CON1 (RESET) is pulled up to 5V through a 10-K
Ω resistor,
and is controlled by the EPM7128AE configuration controller. The
FPGA can cause the configuration controller to assert RESET, but the
FPGA does not drive this signal directly.
Table 2–28 provides CompactFlash pin-out details.
Table 2–28. CompactFlash (CON1) Pin Table (Part 1
of 2)
Pin on
CompactFlash
(CON1)
CompactFlash
Function (U60)
Connects to (1)
1 GND GND
2 D03 AA3
3 D04 AA1
4 D05 Y2
5 D06 W1
6 D07 V2
7 CS0# AE3
8 A10 AF1
9 ATA_SEL# AD12
10 A09 AF3
11 A08 AF4
12 A07 AG1
13 VCC V
CC
(2)
14 A06 AD6
15 A05 AD7
16 A04 AA8
17 A03 AA9
18 A02 AE2
19 A01 AD2
20 A00 AE1
21 DO0 AB3
22 DO1 AB1
23 DO2 Y4
24 IOCS16# AD1
25 CD2# AB8 (3)
26 CD1# AC15