Altera Stratix II EP2S180 DSP Development Board - Manual (Page 55)

Altera Corporation Core Version a.b.c variable 2–47
Stratix II EP2S180 DSP Development Board Reference Manual
Board Components & Interfaces
Expansion Prototype Connector (J23, J24, J25)
Headers J23, J24, and J25 collectively form a standard-footprint,
mechanically stable connection that can be used (for example) as an
interface to a special function daughter card.
f
For a list of available expansion daughter cards that can be used with the
Stratix II EP2S180 DSP development board refer to
www.altera.com/devkits.
The expansion prototype connector interfaces include:
■ 41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins
on the Stratix II device. Each signal passes through analog switches
(U19, U20, U21, U22 and U25) to protect the Stratix II device from 5 V
logic levels. These analog switches are permanently enabled. The
output logic-level on the expansion prototype connector pins is
3.3 V.
■ A buffered, zero-skew copy of the on-board OSC output from U2.
■ A buffered, zero-skew copy of the Stratix II device’s phase-locked
loop (PLL)-output from U60.
■ A logic-negative power-on reset signal.
■ Five regulated 3.3-V power-supply pins (2 A total maximum load for
both connectors.
■ One regulated 5-V power-supply pin (1 A total maximum load for
both connectors.
■ Numerous ground connections.
Figures 2–10 and 2–11 show connections from the expansion prototype
connector to the Stratix II device. Unless otherwise noted, labels indicate
Stratix II device pin numbers.
Figure 2–10. Expansion Prototype Connector - J23, J24, J25
Pin 1
J23
J24
J25
Pin 1
Pin 1