Altera SerialLite II Protocol - Manual (Page 31)

Altera Corporation 31
SerialLite II Protocol Reference Manual
SerialLite II Specification
After reset is complete, the receiver/transmitter transitions to the
character alignment state.
Character Alignment State
In this state, bit lock and symbol alignment is achieved by the
configuration of lane polarity. Support for lane polarity inversion is
optional. The transmitter sends the {|TS1|} sequence across all lanes so
that the receiver can start its initialization process. The receiver aligns to
the incoming /COM/ character from either {|TS1|} or {|TS2|} on a lane
by lane basis across all lanes.
The /COM/ character is followed by seven valid data characters. The last
character of the sequence is used to determine the parity. If any of the
parity identifiers in any lane is either /!T1/ (D21.5) or /!T2/ (D26.5), the
receiver for that lane inverts the polarity (if that option is enabled).
Otherwise, it is considered a catastrophic error.
Once at least four consecutive sequences of a /COM/ character followed
by seven valid data characters with the last character of the sequence
being either /T1/ (D10.2) or /T2/ (D5.2) have been received on each lane,
the receiver/transmitter transitions to the acknowledge character
alignment state.
Acknowledge Character Alignment State
In this state, the transmitter sends the {|TS2|} sequence across all lanes to
inform the remote port that the near receiver is initialized. The receiver
waits until it receives the {|TS2|} sequence on all lanes.
If a deviation from consecutive {|TS1|} sequences to consecutive {|TS2|}
sequences is detected, the receiver/transmitter transitions to the
character alignment state.
Once the receiver detects at least four {|TS2|} sequences on each lane, the
transmitter sends an additional eight {|TS2|} sequences on each lane and
the receiver/transmitter transitions to the lane alignment state.
Lane Alignment State
In this state, lanes are deskewed for multi-lane links and the lane order is
configured. Support for lane reversal is optional. The transmitter sends
the {|TDS|} sequence on all lanes and the receiver adjusts the lanes so it
is simultaneously receiving the /ALN/ character on all lanes. The
receiver also checks that the lane number embedded in the {|TDS|}
sequence is correct. If it is not correct, the lanes are reversed (if that option
is enabled). If the lane ordering remains incorrect, it is considered a
catastrophic error. For lanes to configure correctly into a bonded link the
third character of {|TS2|} representing the transfer size must be the same
across all lanes. Otherwise it is considered a catastrophic error.