Altera SerialLite II Protocol - Manual (Page 9)

Altera Corporation 9
Preliminary
SerialLite II
Specification
Introduction SerialLite II is a lightweight, chip-to-chip protocol suitable for packet and
streaming data in chip-to-chip, board-to-board, and backplane
applications. This protocol offers low protocol overhead, low gate count,
and minimum data transfer latency. It provides reliable, high-speed
transfers of packets between devices over serial links. The SerialLite II
protocol defines packet encapsulation at the link layer and data encoding
at the physical layer. This protocol integrates transparently with existing
networks, without software support.
Protocol Features
■ Simplex and duplex operation
■ Symmetrical and asymmetrical operation
■ In-band control signalling
■ Supports streaming and packet-based protocols
■ Support for two user packet types: data packet and priority packet
■ Nesting (priority packet within data packet) for time-critical control
packet
■ Support for single or multiple lanes
■ Data packet size: minimum one byte; no maximum.
■ Priority packet size: minimum one byte; no maximum
■ 8B/10B Physical layer encoding
■ Synchronous or asynchronous operation
■ Lane polarity reversal
■ Lane-to-lane reordering for multi-lane operation
■ Packet integrity protection using CRC-32 or CRC-16
■ Payload and idle scrambling
■ Link management packets
■ Error detection
■ Segment retry-on-error for priority packets
■ In-band flow control for priority and data packets
■ Low protocol overhead
■ Low point-to-point transfer latency
■ Inter-frame gaps are not required
Typical Applications
■ Packet or streaming data applications
■ Chip-to-chip connectivity
■ Board-to-board connectivity