Link-up state, Clock tolerance compensation, Clock tolerance compensation rules – Altera SerialLite II Protocol User Manual
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Altera Corporation
SerialLite II Protocol Reference Manual
Physical Layer Description
Link-Up State
The link-up state is the normal operation state. User data is transmitted
and received across the established link. This is the only state where link
status indicates link-up.
If a link error is declared, the receiver transitions to the reset state. The
leaky bucket algorithm outlined in the
is used to monitor data errors causing a link error when an
excessive number of data errors are received.
Clock Tolerance Compensation
Clock tolerance compensation is used for asynchronous
implementations. A transmitter and receiver are at the ends of each
physical lane. The transmitter is driven by a reference frequency with a
given tolerance. The receiver, using a phase-locked loop (PLL) recovers
the transmit clock from the incoming data stream. The reference clock for
the receiver PLL is also of the same frequency with a given tolerance. The
worst-case frequency difference between the transmit and receive clocks
of a lane occurs when one is at the fast end of its range and the other is at
the slow end. For clocks with
+/− 300 ppm accuracy, they would be off by
600 ppm, and they would be out of synchronization every 1,666 cycles.
With a tolerance of
+/− 100 ppm, the worst-case scenario has the clocks
going out of synchronization every 5,000 cycles. The following formula
calculates the smallest interval at which the two clocks can remain in
synchronization for a given frequency tolerance.
Clock Offset Frequency Calculation
To compensate for this lack of synchronization, an ‘elastic’ buffer is
placed in the receive path. Data is written into the buffer using the
recovered transmit clock, and data is read out of the buffer using the
receive reference clock. A clock tolerance compensation sequence {|CC|}
is inserted by the transmitter into the data stream at the clock offset
frequency. The ‘elastic’ buffer compensates for the differences between
the two clocks by dropping the {|CC|} sequence. The input side of the
buffer operates in the recovered clock domain; the output side operates in
the receive clock domain. If the recovered clock is faster than the reference
clock, the clock tolerance compensation is satisfied with the removal of
{|CC|}. Otherwise, if the recovered clock is slower than the reference
clock, the receive data path is flow controlled until more data is available.
Clock Tolerance Compensation Rules
The following clock tolerance compensation rules must be followed:
ClockOffsetFrequency
1 000 000
,
,
(
)
2
n
×
(
)
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=