Altera SerialLite II Protocol - Manual (Page 51)

Altera Corporation 51
SerialLite II Protocol Reference Manual
SerialLite II Specification
Figure 2–29. Link Management Packet Alignment
Clock Tolerance Compensation Sequence Alignment
The clock tolerance compensation sequence is inserted at the scheduled
time and may interrupt a partial packet transfer, as shown in
Figure 2–30 .
Figure 2–30. Clock Tolerance Compensation Sequence Alignment
Illegal Multi-Lane Alignment
Figure 2–31 on page 2–52 shows an example of an illegal multi-lane
alignment.
Lane
# 2
Lane
# 3
Time
Lane
# 0
Lane
# 1
IDL
PD0
PD4
EG P1
IDL
PD1
PD5
EG P2
SDP1
PD2
PD6
SDP2
PD3
PD7
CRC1 CRC2
CRC3 CRC4
SLP LD 0 LD 1 LD 2
SPP1 SPP2
D1 D2 D0 D3
D4 D5 D6 D7
D8 D9 D 10
CRC1 CRC2 EG P1 EG P2
IDL IDL IDL IDL
IDL
SUP1 SUP2
CDP1 CDP2
CRC1 CRC2
IDL IDL
Link Management Packet
Lane
# 2
Lane
# 3
Time
Lane
# 0
Lane
# 1
D8
IDL
PD0
PD4
EG P1
D0
D4
IDL
IDL
PD1
PD5
EG P2
D1
D5
SDP1
IDL
PD2
PD6
IDL
D2
D6
SDP2
IDL
PD3
PD7
IDL
D3
D7
CRC1 CRC2
CRC1 CRC2
CRC3 CRC4
EG P1 EG P2
SPP1 SPP2
Clock Tolerance
Compensation
Sequence
IDL IDL
COM
IDL
IDL
IDL
IDL IDL IDL IDL
COM
IDL
IDL
IDL
COM
IDL
IDL
IDL
COM
IDL
IDL
IDL