Chapter 3 – DFI HM920-HM86 User Manual

Page 23

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Chapter 3 Hardware Installation

23

Chapter 3

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Signal

Pin#

Module Pin Type Pwr Rail /Tolerance

HM920

Carrier Board

Description

I2C_CK

B33

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3.3VSB

General purpose I2C port clock output

I2C_DAT

B34

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K to 3.3VSB

General purpose I2C port data I/O line

SPKR

B32

O CMOS

3.3V / 3.3V

Output for audio enunciator - the "speaker" in PC-AT systems.
This port provides the PC beep signal and is mostly intended for
debugging purposes.

WDT

B27

O CMOS

3.3V / 3.3V

Output indicating that a watchdog time-out event has occurred.

Signal

Pin#

Module Pin Type Pwr Rail /Tolerance

HM920

Carrier Board

Description

PWRBTN#

B12

I CMOS

3.3V Suspend/3.3V

PU 10K TO 3.3VSB

PU 4.7K TO 3.3VSB

A falling edge creates a power button event. Power button events can
be used to bring a system out of S5 soft off and other suspend states,
as well as powering the system down.

SYS_RESET#

B49

I CMOS

3.3V Suspend/3.3V

PU 10K TO 3.3VSB

NC PU 4.7K TO 3.3VSB

Reset button input. Active low request for Module to reset and reboot.
May be falling edge sensitive. For situations when SYS_RESET# is
not able to reestablish control of the system, PWR_OK or a power
cycle may be used.

CB_RESET#

B50

O CMOS

3.3V Suspend/3.3V

Reset output from Module to Carrier Board. Active low. Issued by
Module chipset and may result from a low SYS_RESET# input, a low
PWR_OK input, a VCC_12V power input that falls below the minimum
specification, a watchdog timeout, or may be initiated by the Module
software.

PWR_OK

B24

I CMOS

3.3V / 3.3V

PU 10K TO 3.3V

Power OK from main power supply. A high value indicates that the
power is good. This signal can be used to hold off Module startup to
allow Carrier based FPGAs or other configurable devices time to be
programmed.

SUS_STAT#

B18

O CMOS

3.3V Suspend/3.3V

Indicates imminent suspend operation; used to notify LPC devices.

SUS_S3#

A15

O CMOS

3.3V Suspend/3.3V

Indicates system is in Suspend to RAM state. Active low output. An
inverted copy of SUS_S3# on the Carrier Board may be used to
enable the non-standby power on a typical ATX supply.

SUS_S4#

A18

O CMOS

3.3V Suspend/3.3V

Indicates system is in Suspend to Disk state. Active low output.

SUS_S5#

A24

O CMOS

3.3V Suspend/3.3V

Indicates system is in Soft Off state.

WAKE0#

B66

I CMOS

3.3V Suspend/3.3V

PU 1K TO 3.3VSB

PCI Express wake up signal.

WAKE1#

B67

I CMOS

3.3V Suspend/3.3V

PU 10K TO 3.3VSB

General purpose wake up signal. May be used to implement wake-up
on PS2 keyboard or mouse activity.

BATLOW#

A27

I CMOS

3.3V Suspend/ 3.3V

PU 8.2K TO 3.3VSB

Indicates that external battery is low.
This port provides a battery-low signal to the Module for orderly
transitioning to power saving or power cut-off ACPI modes.

THRM#

B35

I CMOS

3.3V / 3.3V

PU 10K TO 3.3V

Input from off-Module temp sensor indicating an over-temp situation.

THRMTRIP#

A35

O CMOS

3.3V / 3.3V

PU 10K TO 3.3V

Active low output indicating that the CPU has entered thermal shutdown.

SMB_CK

B13

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K TO 3.3VSB

NC PU 4.7K TO 3.3VSB

System Management Bus bidirectional clock line.

SMB_DAT

B14

I/O OD CMOS

3.3V Suspend/3.3V

PU 2.2K TO 3.3VSB

NC PU 4.7K TO 3.3VSB

System Management Bus bidirectional data line.

SMB_ALERT#

B15

I CMOS

3.3V Suspend/3.3V

System Management Bus Alert – active low input can be used to
generate an SMI# (System Management Interrupt) or to wake the system.

Signal

Pin#

Module Pin Type Pwr Rail /Tolerance

HM920

Carrier Board

Description

GPO0

A93

GPO1

B54

GPO2

B57

GPO3

B63

GPI0

A54

PU 100K to 3.3V

GPI1

A63

PU 100K to 3.3V

GPI2

A67

PU 100K to 3.3V

GPI3

A85

PU 100K to 3.3V

I CMOS

3.3V / 3.3V

General purpose input pins.
Pulled high internally on the Module.

Power and System Management Signals Descriptions

GPIO Signals Descriptions

O CMOS

General purpose output pins.
Upon a hardware reset, these outputs should be low.

3.3V / 3.3V

Miscellaneous Signal Descriptions

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