Figure11 . mpc860t block diagram, Mpc860t block diagram -4, Freescale semiconductor, inc – Freescale Semiconductor POWERPC MPC860T User Manual

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1-4

MPC860T (Rev. D) Fast Ethernet Controller Supplement

MOTOROLA

PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE

Figure 1-1. MPC860T Block Diagram

The FEC complies with the IEEE 802.3 speciÞcation for 10- and 100-Mbps connectivity.
Full-duplex 100-Mbps operation is supported at system clock rates of 40 MHz and higher.
A 25-MHz system clock supports 10-Mbps operation or half-duplex 100-Mbps operation.

The implementation of bursting DMA reduces bus usage. Independent DMA channels for
accessing BDs and transmit and receive data minimize latency and FIFO depth
requirements.

Transmit and receive FIFOs further reduce bus usage by localizing all collisions to the FEC.
Transmit FIFOs maintain a full collision window of transmit frame data, eliminating the
need for repeated DMA over the system bus when collisions occur. On the receive side, a
full collision window of data is received before any receive data is transferred into system
memory, allowing the FIFO to be ßushed in the event of a runt or collided frame, with no
DMA activity. However, external memory for buffers and BDs is required; on-chip FIFOs
are designed only to compensate for collisions and for system bus latency.

Independent TxBD and RxBD rings in external memory allow nearly unlimited ßexibility

Bus

System Interface Unit (SIU)

Embedded

Parallel I/O

Memory Controller

4 Timers

Interrupt

Controllers

Dual-Port RAM

Serial

and

System Functions

Real-Time Clock

PCMCIA-ATA Interface

4-KByte

Instruction MMU

Data MMU

Instruction

Bus

Load/Store

Bus

Unified

Baud Rate

Generators

Parallel Interface Port

and UTOPIA

MAC

Internal

Bus Interface

Unit

External

Bus Interface

Unit

Timers

32-Bit RISC Controller

and Program

ROM

Serial Interface

I

2

C

SPI

Time Slot Assigner

PowerPC

Processor

Core

DMAs

FIFOs

10/100

MII

Base-T

Media Access

Serial Interface

I

2

C

SPI

Time Slot Assigner

Control

DMA

Channels

Fast

Ethernet

Controller

Instruction Cache

4-KByte

Data Cache

SCC1

SCC2

SCC3

SCC4

SMC1

SMC2

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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