Freescale Semiconductor POWERPC MPC860T - Manual (Page 36)

6-4 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
Table 6-4 describes HASH_TABLE_HIGH Þelds.
6.2.4 RAM Hash Table Low (HASH_TABLE_LOW)
The HASH_TABLE_LOW register, shown in Figure 6-4, contains the lower 32 bits of the
64-bit hash table used in the address recognition process for receive frames with a multicast
address. It is written by and must be initialized by the user.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field HASH_HIGH
Reset UndeÞned
R/W Read/write
Addr 0xE08
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field HASH_HIGH
Reset UndeÞned
R/W Read/write
Addr 0xE0A
Figure 6-3. HASH_TABLE_HIGH Register
Table 6-4. HASH_TABLE_HIGH Field Descriptions
Bits Name Description
0Ð31 HASH_HIGH Contains the upper 32 bits of the 64-bit hash table used in address recognition for receive
frames with a multicast address. HASH_HIGH[0] contains hash index bit 63.
HASH_HIGH[31] contains hash index bit 32.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field HASH_LOW
Reset UndeÞned
R/W Read/write
Addr 0xE0C
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field HASH_LOW
Reset UndeÞned
R/W Read/write
Addr 0xE0E
Figure 6-4. HASH_TABLE_LOW Register
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