Freescale Semiconductor POWERPC MPC860T - Manual (Page 15)

MOTOROLA Chapter 1. Overview 1-5
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
in memory management of transmit and receive data frames. External memory (DRAM) is
inexpensive, and because BD rings in external memory have no inherent size limitations,
memory management easily can be optimized to system needs.
1.4.2 SIU Interrupt ConÞguration
As shown in Figure 1-2, the SIU receives interrupts from internal sources, such as the FEC
and other modules and external pins, IRQ[0Ð7].
Figure 1-2. MPC860T Interrupt Structure
Note that MII_TXCLK is shared with IRQ7 and becomes active as soon as the ETHER_EN
bit in the Ethernet control register (ECNTRL) is set. IRQ7 must be masked in the system
interface unit (SIU).
1.5 Glueless System Design
A fundamental design goal of the MPC8xx family was ease of interface to other system
components. Examples of system design are located in the MPC860T userÕs manual.
Level 2
Level 7
Level 6
Level 5
Level 4
Level 3
Level 1
Level 0
NMI
IRQ[0Ð7]
IREQ
NMI
GEN
PowerPC
TB
PIT
RTC
PCMCIA
CPM Interrupt
SWT
IRQ0
Interrupt Controller
DEC DEC
Debug
Debug
FEC
Controller
System Interface Unit
Edge
Detector
Selector
Core
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