Freescale Semiconductor POWERPC MPC860T - Manual (Page 44)

6-12 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
Table 6-13 describes X_DES_ACTIVE Þelds.
6.2.13 MII Management Frame Register (MII_DATA)
The MII_DATA register, shown in Figure 6-13, is used to communicate with the attached
MII-compatible PHY device, providing read/write access to their MII registers. Writing to
MII_DATA causes a management frame to be sourced unless MII_SPEED was cleared; in
this case, if MII_SPEED is then written to a non-zero value and an MII frame is generated
with the data previously written to MII_DATA. This allows MII_DATA and MII_SPEED
to be programmed in either order if MII_SPEED is currently zero. MII_DATA is accessed
by the user and does not reset to a deÞned value.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ X_DES_ACTIVE Ñ
Reset 0000_0000_0000_0000
R/W Read/write
Addr 0xE54
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ
Reset 0000_0000_0000_0000
R/W Read/write
Addr 0xE56
Figure 6-12. X_DES_ACTIVE Register
Table 6-13. X_DES_ACTIVE Field Descriptions
Bits Name Description
0Р6 С Reserved.
7 X_DES_ACTIVE Set when this register is written, regardless of the value written. Cleared whenever no
additional ready descriptors remain in the transmit ring.
8Р31 С Reserved.
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