Freescale Semiconductor POWERPC MPC860T User Manual
Mpc860t (rev. d) fast ethernet controller
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PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
MPC860TAD/D
Rev. 0.8, 09/1999
ª
MPC860T (Rev. D) Fast Ethernet
Controller
Supplement to the
MPC860 PowerQUICC™ User’s Manual
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For More Information On This Product,
Go to: www.freescale.com
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Table of contents
Document Outline
- MPC860T (Rev. D) Fast Ethernet Controller
- Chapter1 Overview
- Chapter2 FEC External Signals
- Chapter3 Fast Ethernet Controller Operation
- Chapter4 Parallel I/O Ports
- Chapter5 SDMA Bus Arbitration and Transfers
- Chapter6 Programming Model
- 6.1 Overview
- 6.2 Parameter RAM
- Table61 . FEC Parameter RAM Memory Map
- 6.2.1 RAM Perfect Match Address Low Register (ADDR_LOW)
- 6.2.2 RAM Perfect Match Address High (ADDR_HIGH)
- 6.2.3 RAM Hash Table High (HASH_TABLE_HIGH)
- 6.2.4 RAM Hash Table Low (HASH_TABLE_LOW)
- 6.2.5 Beginning of RxBD Ring (R_DES_START)
- 6.2.6 Beginning of TxBD Ring (X_DES_START)
- 6.2.7 Receive Buffer Size Register (R_BUFF_SIZE)
- 6.2.8 Ethernet Control Register (ECNTRL)
- 6.2.9 Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK)
- 6.2.10 Ethernet Interrupt Vector Register (IVEC)
- 6.2.11 RxBD Active Register (R_DES_ACTIVE)
- 6.2.12 TxBD Active Register (X_DES_ACTIVE)
- 6.2.13 MII Management Frame Register (MII_DATA)
- 6.2.14 MII Speed Control Register (MII_SPEED)
- 6.2.15 FIFO Receive Bound Register (R_BOUND)
- 6.2.16 FIFO Receive Start Register (R_FSTART)
- 6.2.17 Transmit Watermark Register (X_WMRK
- 6.2.18 FIFO Transmit Start Register (X_FSTART)
- 6.2.19 DMA Function Code Register (FUN_CODE)
- 6.2.20 Receive Control Register (R_CNTRL)
- 6.2.21 Receive Hash Register (R_HASH)
- 6.2.22 Transmit Control Register (X_CNTRL)
- 6.3 Initialization Sequence
- 6.4 Buffer Descriptors (BDs)
- Chapter7 Electrical Characteristics
- 7.1 DC Electrical Characteristics
- 7.2 AC Electrical Characteristics
- 7.3 Electrical Specifications
- 7.4 MPC860T Pin Assignments