Document Outline

• MPC860T (Rev. D) Fast Ethernet Controller
  • Chapter1 Overview
    • 1.1 Document Revision History
      • Table11 . Document Revision History
    • 1.2 Overview
    • 1.3 Comparison with the MPC860
    • 1.4 Features
      • 1.4.1 MPC860TBlock Diagram
        • Figure11 . MPC860T Block Diagram
      • 1.4.2 SIU Interrupt Configuration
        • Figure12 . MPC860T Interrupt Structure
    • 1.5 Glueless System Design
      • Figure13 . MPC860T Serial Configuration
  • Chapter2 FEC External Signals
    • 2.1 Signal Descriptions
      • Table21 . FEC Signal Descriptions
  • Chapter3 Fast Ethernet Controller Operation
    • 3.1 Transceiver Connection
      • Table31 . MII Signals
      • Table32 . Serial Mode Connections to the External Transceiver
    • 3.2 FEC Frame Transmission
    • 3.3 FEC Frame Reception
    • 3.4 CAM Interface
    • 3.5 FEC Command Set
    • 3.6 Ethernet Address Recognition
      • Figure31 . Ethernet Address Recognition Flowchart
    • 3.7 Hash Table Algorithm
    • 3.8 Inter-Packet Gap Time
    • 3.9 Collision Handling
    • 3.10 Internal and External Loopback
    • 3.11 Ethernet Error-Handling Procedure
      • 3.11.1 Transmission Errors
        • Table33 . Transmission Errors
      • 3.11.2 Reception Errors
        • Table34 . Reception Errors
  • Chapter4 Parallel I/O Ports
    • 4.1 Port D Pin Functions
      • Table41 . Port D Pin Assignment
      • 4.1.1 Port D Registers
      • 4.1.2 Enabling MII Mode
  • Chapter5 SDMA Bus Arbitration and Transfers
    • 5.1 Overview
      • Figure51 . SDMA Bus Arbitration
    • 5.2 The SDMA Registers
      • 5.2.1 SDMA Configuration Register (SDCR)
        • Figure52 . SDMA Configuration Register (SDCR)
        • Table51 . SDCR Field Descriptions
  • Chapter6 Programming Model
    • 6.1 Overview
    • 6.2 Parameter RAM
      • Table61 . FEC Parameter RAM Memory Map
      • 6.2.1 RAM Perfect Match Address Low Register (ADDR_LOW)
        • Figure61 . ADDR_LOW Register
        • Table62 . ADDR_LOW Field Descriptions
      • 6.2.2 RAM Perfect Match Address High (ADDR_HIGH)
        • Figure62 . ADDR_HIGH Register
        • Table63 . ADDR_HIGH Field Descriptions
      • 6.2.3 RAM Hash Table High (HASH_TABLE_HIGH)
        • Figure63 . HASH_TABLE_HIGH Register
        • Table64 . HASH_TABLE_HIGH Field Descriptions
      • 6.2.4 RAM Hash Table Low (HASH_TABLE_LOW)
        • Figure64 . HASH_TABLE_LOW Register
        • Table65 . HASH_TABLE_LOW Field Descriptions
      • 6.2.5 Beginning of RxBD Ring (R_DES_START)
        • Figure65 . R_DES_START Register
        • Table66 . R_DES_START Field Descriptions
      • 6.2.6 Beginning of TxBD Ring (X_DES_START)
        • Figure66 . X_DES_START Register
        • Table67 . X_DES_START Field Descriptions
      • 6.2.7 Receive Buffer Size Register (R_BUFF_SIZE)
        • Figure67 . R_BUFF_SIZE Register
        • Table68 . R_BUFF_SIZE Field Descriptions
      • 6.2.8 Ethernet Control Register (ECNTRL)
        • Figure68 . ECNTRL Register
        • Table69 . ECNTRL Field Descriptions
      • 6.2.9 Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK)
        • Figure69 . I_EVENT/I_MASK Registers
        • Table610 . I_EVENT/I_MASK Field Descriptions
      • 6.2.10 Ethernet Interrupt Vector Register (IVEC)
        • Figure610 . IVEC Register
        • Table611 . IVEC Field Descriptions
      • 6.2.11 RxBD Active Register (R_DES_ACTIVE)
        • Figure611 . R_DES_ACTIVE Register
        • Table612 . R_DES_ACTIVE Field Descriptions
      • 6.2.12 TxBD Active Register (X_DES_ACTIVE)
        • Figure612 . X_DES_ACTIVE Register
        • Table613 . X_DES_ACTIVE Field Descriptions
      • 6.2.13 MII Management Frame Register (MII_DATA)
        • Figure613 . MII_DATA Register
        • Table614 . MII_DATA Field Descriptions
      • 6.2.14 MII Speed Control Register (MII_SPEED)
        • Figure614 . MII_SPEED Register
        • Table615 . MII_SPEED Field Descriptions
        • Table616 . Programming Examples for MII_SPEED Register
      • 6.2.15 FIFO Receive Bound Register (R_BOUND)
        • Figure615 . R_BOUND Register
        • Table617 . R_BOUND Field Descriptions
      • 6.2.16 FIFO Receive Start Register (R_FSTART)
        • Figure616 . R_FSTART Register
        • Table618 . R_FSTART Field Descriptions
      • 6.2.17 Transmit Watermark Register (X_WMRK
        • Figure617 . X_WMRK Register
        • Table619 . X_WMRK Field Descriptions
      • 6.2.18 FIFO Transmit Start Register (X_FSTART)
        • Figure618 . X_FSTART Register
        • Table620 . X_FSTART Field Descriptions
      • 6.2.19 DMA Function Code Register (FUN_CODE)
        • Figure619 . FUN_CODE Register
        • Table621 . FUN_CODE Field Descriptions
      • 6.2.20 Receive Control Register (R_CNTRL)
        • Figure620 . R_CNTRL Register
        • Table622 . R_CNTRL Field Descriptions
      • 6.2.21 Receive Hash Register (R_HASH)
        • Figure621 . R_HASH Register
        • Table623 . R_HASH Field Descriptions
      • 6.2.22 Transmit Control Register (X_CNTRL)
        • Figure622 . X_CNTRL Register
        • Table624 . X_CNTRL Field Descriptions
    • 6.3 Initialization Sequence
      • 6.3.1 Hardware Initialization
        • Table625 . Hardware Initialization
        • Table626 . ECNTRL[ETHER_EN] Deassertion Initialization
      • 6.3.2 User Initialization (before Setting ECNTRL[ETHER_EN])
        • Table627 . User Initialization (before Setting ECNTRL[ETHER_EN])
        • 6.3.2.1 Descriptor Controller Initialization
        • 6.3.2.2 User Initialization (after Asserting ECNTRL[ETHER_EN])
          • Table627 . User Initialization (after Setting ECNTRL[ETHER_EN])
    • 6.4 Buffer Descriptors (BDs)
      • 6.4.1 Ethernet Receive Buffer Descriptor (RxBD)
        • Figure623 . Receive Buffer Descriptor (RxBD)
        • Table627 . Receive Buffer Descriptor (RxBD) Field Description
      • 6.4.2 Ethernet Transmit Buffer Descriptor (TxBD)
        • Figure624 . Transmit Buffer Descriptor (TxBD)
        • Table6-29 . Transmit Buffer Descriptor (TxBD) Field Descriptions
  • Chapter7 Electrical Characteristics
    • 7.1 DC Electrical Characteristics
    • 7.2 AC Electrical Characteristics
    • 7.3 Electrical Specifications
      • 7.3.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, RX_CLK)
        • Figure71 . MII Receive Signal Timing Diagram
        • Table71 . MII Receive Signal Timing
      • 7.3.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
        • Table72 . MII Transmit Signal Timing
        • Figure72 . MII Transmit Signal Timing Diagram
      • 7.3.3 MII Async Inputs Signal Timing (CRS, COL)
        • Table73 . MII Async Inputs Signal Timing
        • Figure73 . MII Async Inputs Timing Diagram
      • 7.3.4 MII Serial Management Channel Timing (MDIO,MDC)
        • Table74 . MII Serial Management Channel Timing
        • Figure74 . MII Serial Management Channel Timing Diagram
    • 7.4 MPC860T Pin Assignments
      • Figure75 . MPC860T Pinout Diagram—Top View