Figure613 . mii_data register, Table614 . mii_data field descriptions, Mii_data register -13 – Freescale Semiconductor POWERPC MPC860T User Manual

Page 45: Mii_data field descriptions -13, Freescale semiconductor, inc

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MOTOROLA

Chapter 6. Programming Model

6-13

PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE

Table 6-14 describes MII_DATA Þelds.

To read or write on the MII management interface, MII_DATA is written by the user. To
generate a valid read or write management frame, ST must be 01, OP must be 01
(management register write frame) or 10 (management register read frame), and TA must
be 10.

To generate an 802.3-compliant MII management interface write frame (write to a PHY
register) the user must write {01 01 PHYAD REGAD 10 DATA} to MII_DATA. Writing
this pattern causes the control logic to shift data out of MII_DATA following a preamble
generated by the control state machine. When the write management frame operation
completes, the MII_DATAIO_COMPL interrupt is generated. At this time the contents of
MII_DATA match the original value written.

To generate an MII management interface read frame (read a PHY register), the user must
write {01 10 PHYAD REGAD 10 XXXX} to MII_DATA, (the content of the DATA Þeld
is a donÕt care). Writing this pattern causes the control logic to shift data out of MII_DATA
following a preamble generated by the control state machine. During this time, the contents
of MII_DATA are serially shifted and are unpredictable if read by the user. An
MII_DATAIO_COMPL interrupt is generated when the read management frame operation

Bits

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Field

ST

OP

PA

RA

TA

Reset

UndeÞned

R/W

Read/write

Addr

0xE80

Bits

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Field

DATA

Reset

UndeÞned

R/W

Read/write

Addr

0xE82

Figure 6-13. MII_DATA Register

Table 6-14. MII_DATA Field Descriptions

Bits

Name

Description

0Ð1

ST

Start of frame delimiter. Must be programmed to 01 for a valid MII management frame.

2Ð3

OP

Operation code. Must be 10 (read) or 01(write) to generate a valid MII management frame.

4Ð8

PA

PHY address. SpeciÞes one of up to 32 attached PHY devices.

9Ð13

RA

Register address. SpeciÞes one of up to 32 registers within the speciÞed PHY device.

14Ð15

TA

Turnaround. Must be programmed to 10 to generate a valid MII management frame.

16Ð31

DATA

Management frame data. Field for data to be written to or read from PHY register.

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Freescale Semiconductor, Inc.

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