Intel SE8500HW4 - Manual (Page 19)

Intel® Server Board Set SE8500HW4 Processor and Chipset
Revision 1.0
Intel order number D22893-001
7
2.1.2 Installation Order
Some processor signals do not have on-die termination and must be terminated at an end
agent. The Intel
®
Server Board Set SE8500HW4 Mainboard was designed with two separate
Front Side Buses (FSBs). For each bus with a processor installed, the first socket on that bus
must be used to ensure proper signal termination. A processor must be installed in socket 1
before socket 2, and socket 3 before socket 4. Refer to Table 2 for processor installation order.
Table 2. Processor Installation Order
Sockets Number of
Processors 1 2 3 4
VRM 10.2
J1F1
VRM 9.1
J1H2
2
VRM
10.2
J3F1
Installed One
Installed Installed Installed
Installed Installed Two
1
Installed Installed Installed Installed
Installed Installed Installed Installed Installed Three
1
Installed Installed Installed Installed Installed Installed
Four Installed Installed Installed Installed Installed Installed Installed
1. There is no performance gained by splitting the processors across the FSBs. Intel has
validated sequential process installation, with a one-processor configuration using
socket 1; a two-processor configuration using sockets 1 and 2; and a three-processor
configuration using sockets 1, 2 and 3.
2. The 9.1 VRM is only required when installing 64-bit Intel ® Xeon™ Processors MP with
up to 8MB of L3 cache.