Figure 7. server management block diagram – Intel SE8500HW4 User Manual
Page 40
Server Management
Intel® Server Board Set SE8500HW4
Revision
1.0
Intel order number D22893-001
28
BASEBOARD
PROCESSOR SOCKETS(4)
SMS
I/F
System LPC Bus
5V
12V
3.3V
-12V
Po
w
e
r B
u
tt
o
n
F
ront
P
a
ne
l
SD
I Sw
it
ch
Thermal Trip
- Chassis ID
- Baseboard ID
- Power State
CPU Voltage
INTELLIGENT PLATFORM MANAGEMENT BUS (IPMB)
Re
s
e
t B
u
tt
o
n
P
o
wer Connect
o
r
To Power
Distribution
Board
Baseboard
Temp 1
Pri
v
at
e
M
a
n
a
g
e
m
ent
Busses
RAM
CODE
(updateable)
Non-volatile, read-write storage
SENSOR
DATA
RECORDS
SYSTEM
EVENT
LOG
FRU INFO
& CONFIG
DEFAULTS
SMM
I/F
CO
M 1
C
O
MM
MU
X
BBD COM1
CPU FRU
CPU 'Core' Temp
FRU EEPROM
EMP
DIMM SPD (16)
CPU OEM NV
Po
we
r L
E
D
Syst
em
S
tat
u
s
LE
D
FANs (6)
Ne
tw
o
rk
A
c
ti
v
it
y
L
E
D
s
PCI PME
BASEBOARD
MANAGEMENT
CONTROLLER
(BMC)
System I/F
PORTS
1.25V
3.3V Standby
LVDS-B Term
LVDS-A Term
D
riv
e
A
c
ti
v
ity
/F
a
u
lt
L
E
D
Syst
em
I
dent
if
y
But
ton
Hot-swap
Backplane
Header
Aux. IPMB
Connector
Chip Set
ICMB
Transceiver
Header
Logic 2.5V
spkr
Id
e
n
tif
y
L
E
D
Temp Sensor
DUAL
NIC
TCO
FRU EEPROM
Front Panel Connectors
IMM
Figure 7. Server Management Block Diagram
Note: The interconnections and blocks shown are to illustrate the functional relationships
between the system management elements. They do not map directly to the exact circuit
implementation of the architecture.