Intel SE8500HW4 - Manual (Page 35)

Intel® Server Board Set SE8500HW4 Intel® Server Board Set SE8500HW4 Memory Board
Revision 1.0
Intel order number D22893-001
23
4.4 Data Correction and Scrubbing
The XMB employs a Single Device Data Correction (x8 SDDC) algorithm for the memory
subsystem that will recover from a component failure during read and write transactions. This
corrects and logs a correctable memory error, and logs uncorrectable memory errors.
A patrol scrub can be turned on in the system BIOS that scrubs roughly 64GB of memory
behind each XMB every day. The patrol scrub confirms the data for one cache line every 16k
core cycles and then increments the address one cache line. During patrol scrub, an erroneous
read will be logged and re-read. If the re-read is correctable, it is corrected (scrubbed) in
memory. A conflicting read or write request pending issue will be held until the scrub is finished.
4.5 Memory Board Components
DIMM_1B
DIMM_1A
DIMM_2B
DIMM_2A
E8500 eXtended Memory
Bridge
Channel A Channel B
IMI
FRU
I 2 C
Main Board Connector
Remote
Temperature
Sensor
Temperature
Sensor
Controller
Figure 6. Memory Board Block Diagram