IBM HANDBOOK 260 - Manual (Page 41)

Hardware Overview 23
• In a high performance platform, with multiple processors and multiple
memories, a switch may be employed to allow multiple parallel accesses
by the processors to memory. The path through the switches would be
decided by the addressing of memory.
Figure 7. General Platform Topology
Primary Processor Bus/Switch
System Memory Host Bridge
Secondary Bus (PCI)
. . .
. . . . . .
. . . PowerPC Processor
(L1/L2 Cache)
PowerPC Processor
(L1/L2 Cache)
Tertiary Bus (ISA or PCI)
I/O Device I/O Device
. . .
I/O Device I/O Device
Bus
Bridge