IBM HANDBOOK 260 - Manual (Page 65)

Hardware Overview 47
Thus, false sharing increases cache misses and bus traffic, and this may
cause the SMP throughput to be reduced. The bigger the size of the cache
line, the higher the miss rate. Some implementations have a 256-byte cache
line. Both 64-byte and 128-byte cache line sizes are supported by the IBM
SMP design, and these cache line sizes are equivalent to the coherency size
of the system.