IBM HANDBOOK 260 - Manual (Page 58)

40 RS/6000 43P 7043 Models 150 and 260 Handbook
The main memory is the third level of memory. Its access time is slow in
comparison to L1 and L2, but much faster than disks. Twenty to fifty CPU
clock cycles are needed to load data from the memory, and the capacity can
reach several gigabytes.
Figure 12 shows the relationship between proximity of memory to the
processor versus the number of cycles required to access it.
Figure 12. Memory Hierarchy
2.5.1.1 Cache Hit versus Cache Miss
When a CPU fetches a memory address, if the data is found in the cache, it is
a cache hit. Otherwise, it is a cache miss. If a cache miss occurs, the data is
loaded from main memory to the CPU and stored in the cache to take
advantage of the higher speed of the cache for a future fetch of the same
memory address. The hit ratio is the percentage of cache hits. Logically, the
higher the hit ratio, the better the system performance. All RISC System/6000
computers use a scheme called
set associativity to reduce the number of cache
misses.
L1 Cache
1 cycle 32-64 KB
Processor
20-100 cycles
n X GBs
2-10 cycles
L2 Cache
Memory
750 K - 1.5 M cycles n X TBs
Disk
256 KB - 4 MB