IBM HANDBOOK 260 - Manual (Page 55)

Hardware Overview 37
The two additional execution units give POWER3 a peak instruction rate of
eight instructions per cycle (two floating-point, two load/store, two
single-cycle integer, a multi-cycle integer, and a branch instruction).
Significant investments in the chip’s memory interface have been made in
order for the POWER3 to have a sustainable execution rate of four
instructions per cycle (two load instructions and two floating-point). Although
its 64 KB data cache is only half the size of the P2SC’s, its advanced core, a
dedicated second level (L2) cache, and aggressive prefetching mechanisms
improve the memory access speed. The initial POWER3 implementation
applies 4 MB (L2) cache.
POWER3 is defined by the following specifications:
• POWER3 microprocessor running at:
– 200 MHz on RS/6000 Model 260
• Superscalar design with integrated integer, floating-point, and branch units
• 32 KB instruction cache
• 64 KB 128-way set associative data cache
• 64-bit memory interface with 64-bit addressing
• Real memory support for up to 4 GB (3 GB on AIX 4.2.1)
2.4.2 The PowerPC 604e Microprocessor
The RS/6000 43P 7043 Model 150 workstation features the PowerPC 604e
microprocessor. The 604e is an equivalent, but enhanced derivative of the
604. Enhancements to the PowerPC 604e, exceeding its predecessor
(PowerPC 604), include:
• Doubled L1 cache (instruction and data)
• Higher clock frequencies
• Built-in performance monitor
The superscalar design of the 604e provides up to four instructions to be
dispatched per cycle and four to complete at once, with one store and one
branch per cycle.
Figure 11 on page 38 shows the PowerPC 604e microprocessor architecture.