Jameco Electronics Rabbit 3000 - Manual (Page 196)

User’s Manual 187
12.8 Synchronous Communications on Ports E and F
Serial Port E and F are a dual-function serial ports that can be used in either asynchronous
or HDLC mode. Four bytes of buffering are available for both receiver and transmitter to
reduce interrupt overhead. An interrupt is generated whenever at least one byte is avail-
able in the receiver buffer and every time a byte is removed from the transmitter buffer.
Serial Port E is clocked by the output of Timer A2 and Serial Port F by A3. In asynchro-
nous mode this clock can be either sixteen (the default) or eight times the data rate. In
HDLC mode this clock is sixteen times the data rate. Note that the fastest output from
Timer A2 or A3 is the same frequency as the peripheral clock. Thus the maximum data
rate is the peripheral clock frequency divided by eight in async mode and divided by six-
teen in HDLC mode.
The HDLC receiver employs a Digital Phase-Locked-Loop (DPLL) to generate a synchro-
nized receive clock for the incoming data stream. HDLC mode also allows for an external
1x (same speed as the data rate) clock for both the receiver and the transmitter. HDLC
receive and transmit clocks can be input or output, as appropriate, via the specified pins.
When using an external clock, the maximum data rate is one-sixth of the peripheral clock
rate.
In asynchronous mode the port can send and receive seven or eight bits and has the option
of appending and recognizing an additional address bit. On transmit, the address bit is
automatically appended to the data when this data is written to the address register or long
stop register. Writing to the address register appends an “zero” address bit to the data,
while writing to the long stop register appends an “one” address bit to the data. The
address bit is followed by a normal stop bit. Normal data is written to the data register to
be transmitted. On receive, a status bit distinguishes normal data from “address” data. This
status bit is set to one if a “zero” address bit is received. In non-address bit applications,
this indicates a framing error. This status bit can also indicate a received break, if the
accompanying data is all zeros (this is the definition of break). Asynchronous mode oper-
ates full-duplex. Either the receive data available, transmit buffer empty or transmit idle
conditions can be programmed to generate an interrupt.
The HDLC mode allows full-duplex synchronous communication. Either an internal or
external clock may be selected for both the receiver and the transmitter. HDLC mode
encapsulates data within opening and closing Flags, and sixteen bits of CRC precedes the
closing Flag. All information between the opening and closing Flag is "zero-stuffed". That
is, if five consecutive ones occur, independent of byte boundaries, a zero is automatically
inserted by the transmitter and automatically deleted by the receiver. This allows a Flag
byte (0x07E) to be unique within the serial bit stream. The standard CRC-CCITT polyno-
mial (x
16
+ x
12
+ x
5
+ 1) is implemented, with the generator and checker preset to all ones.
Both receive and transmit operation are essentially automatic. In the receiver, each byte is
marked with status to indicate end-of-frame, short frame and CRC error. The receiver
automatically synchronizes on Flag bytes and presets the CRC checker appropriately. If