Figures – National Instruments Isolated Analog Input Device NI PXI-4224 User Manual

Page 7

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Contents

© National Instruments Corporation

vii

NI PXI-4224 User Manual

Figures

Figure 2-1.

NI PXI-4224 Front Label ......................................................................2-3

Figure 2-2.

Unshielded Floating Signal Source Connection
Using a D-SUB Connector ....................................................................2-4

Figure 2-3.

Unshielded Grounded Signal Source Connection
Using a D-SUB Connector ....................................................................2-5

Figure 2-4.

Shielded Floating Signal Source Connection
Using a D-SUB Connector ....................................................................2-6

Figure 2-5.

Shielded Grounded Signal Source Connection
Using a D-SUB Connector ....................................................................2-7

Figure 2-6.

Unshielded Floating Signal Source Connection
Using a Terminal Block ........................................................................2-8

Figure 2-7.

Unshielded Grounded Signal Source Connection
Using a Terminal Block ........................................................................2-9

Figure 2-8.

Shielded Floating Signal Source Connection
Using a Terminal Block ........................................................................2-10

Figure 2-9.

Shielded Grounded Signal Source Connection
Using a Terminal Block ........................................................................2-11

Figure 4-1.

Block Diagram of NI PXI-4224 ............................................................4-2

Figure 4-2.

Effect of Input Impedance on Signal Measurements ............................4-4

Figure 4-3.

AI CONV CLK Signal Routing ............................................................4-6

Figure 4-4.

NI PXI-4224 PXI Trigger Bus Signal Connection................................4-8

Figure 5-1.

Typical Program Flowchart...................................................................5-2

Figure 5-2.

General Synchronizing Flowchart.........................................................5-9

Figure A-1.

PXI-4224 Dimensions ...........................................................................A-4

Figure B-1.

Typical Posttriggered Sequence ............................................................B-2

Figure B-2.

Typical Pretriggered Sequence..............................................................B-2

Figure B-3.

AI START TRIG Input Signal Timing .................................................B-3

Figure B-4.

AI START TRIG Output Signal Timing...............................................B-3

Figure B-5.

AI REF TRIG Input Signal Timing.......................................................B-4

Figure B-6.

AI REF TRIG Output Signal Timing ....................................................B-5

Figure B-7.

AI SAMP CLK Input Signal Timing ....................................................B-6

Figure B-8.

AI SAMP CLK Output Signal Timing..................................................B-6

Figure B-9.

AI CONV CLK Input Signal Timing ....................................................B-7

Figure B-10.

AI CONV CLK Output Signal Timing .................................................B-8

Figure B-11.

AI SAMPLE CLK TIMEBASE Signal Timing ....................................B-9

Figure B-12.

AI HOLD COMPLETE Signal Timing.................................................B-10

Figure C-1.

Injector/Ejector Handle Position Before Device Removal....................C-2

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