Synchronous dram timing (continued) – Texas Instruments TMS320C6712D User Manual

Page 79

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TMS320C6712D

FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

79

POST OFFICE BOX 1443

HOUSTON, TEXAS 77251−1443

SYNCHRONOUS DRAM TIMING (CONTINUED)

ECLKOUT

CE[3:0]

BE[1:0]

EA[21:13]

ED[15:0]

EA12

AOE/SDRAS/SSOE†

ARE/SDCAS/SSADS†

AWE/SDWE/SSWE†

EA[11:2]

Bank

11

12

5

5

1

DEAC

11

12

4

4

1

† ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 34. SDRAM DEAC Command

ECLKOUT

CE[3:0]

BE[1:0]

EA[21:2]

ED[15:0]

EA12

AOE/SDRAS/SSOE†

ARE/SDCAS/SSADS†

AWE/SDWE/SSWE†

8

12

1

REFR

8

12

1

† ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 35. SDRAM REFR Command

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