External interrupt timing, See figure 40) – Texas Instruments TMS320C6712D User Manual

Page 85

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TMS320C6712D

FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

85

POST OFFICE BOX 1443

HOUSTON, TEXAS 77251−1443

EXTERNAL INTERRUPT TIMING

timing requirements for external interrupts

(see Figure 40)

NO.

−150

UNIT

NO.

MIN

MAX

UNIT

1

tw(ILOW)

Width of the NMI interrupt pulse low

2P

ns

1

tw(ILOW)

Width of the EXT_INT interrupt pulse low

4P

ns

2

tw(IHIGH)

Width of the NMI interrupt pulse high

2P

ns

2

tw(IHIGH)

Width of the EXT_INT interrupt pulse high

4P

ns

† P = 1/CPU clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns.

2

1

EXT_INT, NMI

Figure 40. External/NMI Interrupt Timing

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