Busreq timing – Texas Instruments TMS320C6712D User Manual

Page 82

Advertising
background image

TMS320C6712D

FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

82

POST OFFICE BOX 1443

HOUSTON, TEXAS 77251−1443

BUSREQ TIMING

switching characteristics over recommended operating conditions for the BUSREQ cycles
(see Figure 38)

NO.

PARAMETER

−150

UNIT

NO.

PARAMETER

MIN

MAX

UNIT

1

td(EKOH-BUSRV)

Delay time, ECLKOUT high to BUSREQ valid

1.5

7.2

ns

ECLKOUT

1

BUSREQ

1

Figure 38. BUSREQ Timing

Advertising