Jtag test-port timing – Texas Instruments TMS320C6712D User Manual
Page 97
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TMS320C6712D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS293 − OCTOBER 2005
97
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 49)
NO.
−150
UNIT
NO.
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
35
ns
3
tsu(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high
10
ns
4
th(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
7
ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 49)
NO.
PARAMETER
−150
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
15
ns
TCK
TDO
TDI/TMS/TRST
1
2
3
4
2
Figure 49. JTAG Test-Port Timing
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