Rockwell Automation SA500 Diagnostics, Troubleshooting Guide - Manual (Page 43)

Interlock Register C-1
A
PPENDIX
C
Interlock Register
,QWHUORFN 5HJLVWHU 
Interlock tests are executed whenever bit 0 or 1 of register 100/1100 is set. The first problem detected will be
indicated by the identifying bit in this register. Note that these bits will prevent the vector or brushless minor
loop from running.
Configuration Parameters Not Loaded Bit 0
The Configuration Parameters Not Loaded
bit is set if:
+H[ 9DOXH +
6XJ 9DU 1DPH ,&B&1)#
$FFHVV 5HDG RQO\
8'& (UURU &RGH 1$
/(' 1$
• the configuration parameters have not been downloaded into the UDC module
from the Programming Executive, or
• the alignment test has been enabled (register 100/1100, bit 1) when an induction
motor has been configured.
Gains Not Loaded Bit 1
The Gains Not Loaded bit is set if the
required pre-defined local tunables are zero
or if a UDC task containing these tunables
has not been loaded to the PMI. +H[ 9DOXH +
6XJ 9DU 1DPH ,&B*$,1#
$FFHVV 5HDG RQO\
8'& (UURU &RGH 1$
/(' 1$
RPI Missing Bit 2
The RPI Missing bit is set if the Run
Permissive input on the Power Module is not
on.
+H[ 9DOXH +
6XJ 9DU 1DPH ,&B53,#
$FFHVV 5HDG RQO\
8'& (UURU &RGH 1$
/(' 1$
Faults Need Reset Bit 3
The Faults Need Reset bit is set if previous
faults (register 202/1202) have not been
cleared. +H[ 9DOXH +
6XJ 9DU 1DPH ,&B)/7#
$FFHVV 5HDG RQO\
8'& (UURU &RGH 1$
/(' 1$