Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement - Manual (Page 3)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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E XTENDED I NTERRUPT E NABLE (EIE) ....................................................................................................................... 82
MOVX E XTENDED A DDRESS R EGISTER (MXAX)...................................................................................................... 82
CAN 1 M ESSAGE C ENTER 1 C ONTROL R EGISTER (C1M1C)..................................................................................... 83
CAN 1 M ESSAGE C ENTER 2 C ONTROL R EGISTER (C1M2C)..................................................................................... 86
CAN 1 M ESSAGE C ENTER 3 C ONTROL R EGISTER (C1M3C)..................................................................................... 86
CAN 1 M ESSAGE C ENTER 4 C ONTROL R EGISTER (C1M4C)..................................................................................... 86
CAN 1 M ESSAGE C ENTER 5 C ONTROL R EGISTER (C1M5C)..................................................................................... 86
B R EGISTER (B) ...................................................................................................................................................... 87
CAN 1 M ESSAGE C ENTER 6 C ONTROL R EGISTER (C1M6C)..................................................................................... 87
CAN 1 M ESSAGE C ENTER 7 C ONTROL R EGISTER (C1M7C)..................................................................................... 87
CAN 1 M ESSAGE C ENTER 8 C ONTROL R EGISTER (C1M8C)..................................................................................... 87
CAN 1 M ESSAGE C ENTER 9 C ONTROL R EGISTER (C1M9C)..................................................................................... 88
CAN 1 M ESSAGE C ENTER 10 C ONTROL R EGISTER (C1M10C)................................................................................. 88
E XTENDED I NTERRUPT P RIORITY (EIP)..................................................................................................................... 88
CAN 1 M ESSAGE C ENTER 11 C ONTROL R EGISTER (C1M11C)................................................................................. 89
CAN 1 M ESSAGE C ENTER 12 C ONTROL R EGISTER (C1M12C)................................................................................. 89
CAN 1 M ESSAGE C ENTER 13 C ONTROL R EGISTER (C1M13C)................................................................................. 89
CAN 1 M ESSAGE C ENTER 14 C ONTROL R EGISTER (C1M14C)................................................................................. 90
CAN 1 M ESSAGE C ENTER 15 C ONTROL R EGISTER (C1M14C)................................................................................. 90
ADDENDUM TO SECTION 5: CPU TIMING ...........................................................................................91
SYSTEM CLOCK SELECTION............................................................................................................................. 91
C HANGING THE S YSTEM C LOCK /M ACHINE C YCLE C LOCK F REQUENCY ....................................................................... 92
ADDENDUM TO SECTION 6: MEMORY ACCESS ................................................................................93
EXTERNAL MEMORY INTERFACING................................................................................................................. 93
U SING THE COMBINED CHIP - ENABLE SIGNALS ............................................................................................................ 94
I MPLEMENTING A BOOTLOADER USING INTERNAL SRAM ............................................................................................ 95
E XAMPLE DS80C390 M EMORY C ONFIGURATION ...................................................................................................... 95
ADDENDUM TO SECTION 7: POWER MANAGEMENT......................................................................100
P OWER M ANAGEMENT M ODES ............................................................................................................................... 100
S WITCHING BETWEEN CLOCK SOURCES ................................................................................................................... 100
ADDENDUM TO SECTION 8: RESET CONDITIONS ...........................................................................101
RESET SOURCES.............................................................................................................................................. 101
P OWER - ON /F AIL R ESET ......................................................................................................................................... 101
W ATCHDOG T IMER R ESET ...................................................................................................................................... 101
E XTERNAL R ESET .................................................................................................................................................. 102
RESET OUTPUTS .............................................................................................................................................. 102
RESET STATE .................................................................................................................................................... 102
IN-SYSTEM DISABLE MODE............................................................................................................................. 103
ADDENDUM TO SECTION 10: PARALLEL I/O...................................................................................104
P ORT 1 ................................................................................................................................................................. 104
P ORTS 4 AND 5...................................................................................................................................................... 104
OUTPUT FUNCTIONS........................................................................................................................................ 105
ADDENDUM TO SECTION 11: PROGRAMMABLE TIMERS ..............................................................106
D IVIDE -B Y -13 O PTION ........................................................................................................................................... 110
P ROGRAMMABLE C LOCK O UTPUT ........................................................................................................................... 110
I R DA C LOCK O UTPUT ............................................................................................................................................ 111
ADDENDUM TO SECTION 12: SERIAL I/O..........................................................................................112
ADDENDUM TO SECTION 13: TIMED ACCESS PROTECTION.........................................................113
ADDENDUM TO SECTION 16: INSTRUCTION SET DETAILS............................................................114
16-BIT (8051 STANDARD) ADDRESSING MODE............................................................................................. 114
22-BIT PAGED ADDRESSING MODE ............................................................................................................... 114
22-BIT CONTIGUOUS ADDRESSING MODE ................................................................................................... 116