Can 0 receive error register (c0re), Interrupt enable (ie), Can 0 r – Maxim Integrated High-Speed Microcontroller Users Guide: DS80C390 Supplement User Manual
Page 44: Eceive, Rror, Egister, C0re), Nterrupt, Nable
High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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CAN 0 RECEIVE ERROR REGISTER (C0RE)
7 6 5 4 3 2 1 0
SFR A7h
R*-0 R*-0 R*-0 R*-0 R*-0 R*-0 R*-0 R*-0
R= Unrestricted Read, * = Write only by C0TE register, -n = Value after Reset
C0RE.7-0
Bits 7-0
CAN 0 Receive Error Register. This register indicates the number of
accumulated CAN 0 receive errors. All writes to the C0TE register are
simultaneously loaded into this register. This register is cleared following all
hardware Resets and software resets enabled by the CRST bit in the CAN 0
Control Register.
INTERRUPT ENABLE (IE)
7 6 5 4 3 2 1 0
SFR
A8h
EA ES1 ET2 ES0 ET1 EX1 ET0 EX0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R= Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
EA
Bit 7
Global Interrupt Enable. This bit controls the global masking of all interrupts
except Power-Fail Interrupt, which is enabled by the EPFI bit (WDCON.5).
0 = Disable all interrupt sources. This bit overrides individual interrupt mask
settings.
1 = Enable all individual interrupt masks. Individual interrupts will occur if
enabled.
ES1
Bit 6
Enable Serial Port 1 Interrupt. This bit controls the masking of the serial port 1
interrupt.
0 = Disable all serial port 1 interrupts.
1 = Enable interrupt requests generated by the RI_1 (SCON1.0) or TI_1
(SCON1.1) flags.
ET2
Bit 5
Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt.
0 = Disable all Timer 2 interrupts.
1 = Enable interrupt requests generated by the TF2 flag (T2CON.7).
ES0
Bit 4
Enable Serial Port 0 Interrupt. This bit controls the masking of the serial port 0
interrupt.
0 = Disable all serial port 0 interrupts.
1 = Enable interrupt requests generated by the RI_0 (SCON0.0) or TI_0
(SCON0.1) flags.
ET1
Bit 3
Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
0 = Disable all Timer 1 interrupts.
1 = Enable all interrupt requests generated by the TF1 flag (TCON.7).
EX1
Bit 2
Enable External Interrupt 1. This bit controls the masking of external interrupt
1.
0 = Disable external interrupt 1.
1 = Enable all interrupt requests generated by the
1
INT pin.